Although systems based on intermediate layers can be created today, the tools and methodologies are not yet perfected, and there is a mismatch with organizations.

The flaws in the EDA toolchain for 2.5D design limit the application of this advanced packaging method, which is currently mainly confined to the high-performance computing sector. However, as other parts of the chip industry begin to move towards advanced packaging and chiplet components, the EDA industry is starting to adjust its development direction.

All new technologies have a learning period, and 2.5D advanced packaging technology is no exception. Despite the clear potential of this packaging method—featuring more functions than a retina-sized SoC, lower power consumption, and higher performance—the EDA industry is quite cautious about this market. Until recently, it was unclear which of the many packaging solutions would gain enough market share to support investment. However, with the financial market anticipating a larger scale of high bandwidth memory (HBM) applications and the progress of 2.5D technology leading to the first proof of concept, the market situation has seen positive changes.

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To achieve widespread application of 2.5D technology, a significant amount of optimization and automation work is still needed, and the question of which of the various possible solutions will prevail remains to be resolved. However, as standards are gradually released and the industry continues to advance this packaging technology, the related tools need to be more efficient and elegant in addressing a range of challenges than they are currently.

Interfaces

2.5D integration introduces a type of connection that did not previously exist, which is one of the biggest challenges but also an opportunity. While previous designs had the same on-chip connections, 2.5D uses an intermediary for connection. From this perspective, they are quite similar to PCBs (printed circuit boards), but with a connection density closer to that of the most advanced planar chips.

John Park, Group Director of Product Management for Custom IC and PCB at Cadence, said, "When you start making standalone chiplet components and insert PHYs for UCIe, you face the classic issue of signal integrity. When you connect the UCIe interface on this chiplet component to another UCIe interface through an intermediate layer or bridge, does it meet the requirements? How much jitter is there? Is there too much noise on the line causing my receiving eye to narrow? The processing done on the chip design side and the system side is gradually converging. The system side already has over 30 years of experience in dealing with signal integrity, and we have advanced three-dimensional electromagnetic field solvers that allow you to model it. For digital chip designers, this concept may be somewhat novel."Today, integrated circuit designers use tools that are more akin to printed circuit board (PCB) tools, but over time, this will evolve to be more like chip-level issues. Ansys's Director of Product Marketing, Marc Swinnen, stated: "The current communication is still very similar to PCBs, which is coarse-grained. The industry is moving towards finer granularity, and we see chip component connections evolving from C4 bumps to microbumps, to hybrid bonding, with interconnect density increasing as well. With finer granularity and 3D architectures, you can consider the communication between functional modules and other modules. In theory, it can go even further, but designing and laying out with existing tools is just too difficult."

There is a learning curve involved, which includes the development of socket materials and designs, as well as related communication standards. Eliyan's CEO and co-founder, Ramin Farjadrad, said: "UCIe comes in two versions, advanced packaging and standard packaging. For advanced packaging, the wire distance is 2 millimeters; but for standard packaging, the distance is 20 to 25 millimeters. To achieve the highest bandwidth, it is much more difficult to use standard packaging than advanced packaging. In advanced packaging, basic SerDes can achieve 32Gbps. There is no need to worry about crosstalk or channel return loss. Due to the high wire density, you can place high-speed wires within the wire shield without additional vias. In standard packaging, vias must be used, which leads to crosstalk and reflection."

Despite the apparent inclination towards supporting advanced packaging, the reality is not so simple. Farjadrad added: "Although the wire density may be 5 to 6 times lower than that of high-end substrates, this means that the cross-sectional thickness of the wires can be increased by 5 to 6 times. This results in a 30-fold reduction in resistance for the same wire, enabling longer-distance transmission. This is a balanced compromise between high speed and low resistance."

UCIe advanced packaging relies on its very short transmission distances. Tony Mastroianni, Director of Advanced Packaging Solutions at Siemens Digital Industries Software, said: "Therefore, you do not need to use advanced equalization techniques from many long-distance SerDes. This results in smaller size and lower power consumption. They are ideal transmitters and receivers, thus avoiding distortion issues in the packaging wiring channels. You do indeed need to carefully arrange these wirings and address spacing and shielding issues to ensure that performance is not lost due to non-ideal wiring between chips. Most existing PHY designs take advantage of their short-distance characteristics. This creates a problem because you can only place a small amount of HBM memory on one chip. You cannot place them too far from a small chip because these PHYs are not designed for that."

Other tools require significant upgrades. Andy Heinig, head of the High-Efficiency Electronics division at Fraunhofer IIS/EAS, said: "3D systems include vast power distribution networks in different parts of the system. There are grids on the chips, copper pillars or hybrid bonding pads between chips, and other elements outside the system—usually the packaging substrate. The entire power network is a very complex structure, containing millions of design elements of varying sizes. The design elements on the chips are in the range of tens of micrometers, while the structures on the packaging can be as large as several millimeters. For 3D solvers, such multi-level problems are usually difficult to solve, but it is necessary to simulate the entire power grid to verify the power network."

Power issues are more akin to integrated circuit tools than printed circuit board tools. Mastroianni said: "Power is typically provided from the underlying transistors and passed upwards, although related tools can assist, it still needs to be managed. In 3D designs, the entire device will use millions or tens of millions of hybrid bonding fillers. Compared to traditional chips that pre-design power and ground networks, you only need to configure a unified grid across the entire chip to manage power. Placement and routing tools will determine which contacts are used for power transmission."

Variability Issues

As systems evolve towards 2.5D and 3D, on-chip variability (OCV) issues become more pronounced. Mastroianni stated: "Timing closure and OCV have become significant challenges. Since reliance on a single wafer is no longer the case, process variability will be greatly exacerbated. If microchip modules are manufactured using different processes, they will lose their correlation. For a single transistor, you rely on its internal correlation; however, when different technologies, suppliers, and wafers are used, this correlation disappears."

It's not just process variations that need attention, but also temperature changes. Swinnen of Ansys said: "Temperature fluctuations can cause significant device behavior changes beyond the minimum/maximum temperature range of static timing analysis. Mechanical stress has a significant impact on the electrical parameters of semiconductor devices. In fact, many processes intentionally introduce mechanical stress during transistor manufacturing to affect their characteristics. Solutions that translate mechanical results into electrical impacts are still being developed. Additionally, some are focusing on integrating photonics into the packaging, but photonic circuits are very sensitive to temperature, and even minor changes can lead to parameter failure."Corner issues can influence each other. Cadence's Park stated: "To address timing problems, one must consider multiple aspects, such as process, power supply, and thermal management. As these issues stack up, the complexity of the problems also increases. How to solve them? We already have some techniques to mitigate corner issues. When we apply 3D stacking and hybrid bonding, the industry hopes to see similar processes, close nodes, and similar timing performance, thereby achieving more manageable solutions."

In the past, we dealt with variability issues by increasing margins. Mastroianni said: "If you try to address all process variations and performance issues, too much margin will make the design extremely complex. Therefore, we need to set interfaces between modules to fundamentally achieve high-speed synchronization. This can decouple these variations and achieve a highly synchronized high-speed interface between the two modules."

The development of tools

The EDA industry is working hard to solve these and other issues. Kent Stahn, Senior Manager of Hardware Engineering at Synopsys Solutions Group, said: "In this field, there are some packaging-centric tools trying to solve all the problems. At the same time, some tools originating from the silicon field are also continuously evolving to cope with the future, such as RDL fan-out packaging. From a layout perspective, these tools are constantly advancing. Next is the analysis part, where we see the integration between analysis tools and layout tools becoming increasingly excellent."

However, there is still much work to be done. Park said: "At present, the vast majority of tools are extensions of packaging design tools. More than 75% of silicon spacers are made using tools that have been modified in the field of printed circuit boards and laminated packaging over the past few decades. These tools have been adjusted for power. We need a different power router, so we added this feature. However, when I do laminated packaging, there is no formal DRC or LVS. They run some CAM tools to ensure there are no spacing violations and sharp angle problems, but this method is quite informal. We do not manufacture chips in this way. We use a very formal DRC and LVS process to ensure that the results are neat and manufacturable."

The check-out process has been deeply integrated into the chip development method. Swinnen asked: "Why do people trust the check-out process so much? When 3-nanometer technology came out, no one had much experience, and the same is true for 3D interconnects. Everyone acknowledges that the actual application of solvers is still rare. You need a solver that has shown in the past that it can handle unexpected situations properly, with good adaptability, a wide range of applications, and sufficient accuracy. This is also one of the reasons why people are so conservative and reluctant to change in the check-out process. They hope that the solver can correctly and reliably deal with all kinds of problems.

One of the key upgrade requirements is to analyze factors beyond resistance R and capacitance C. Synopsys' Stahn said: "Chip designers often overlook inductance L, which is actually very important. This is why packaging designers, chip designers, and printed circuit board designers need to work together, with multiple disciplines collaborating. There are some different tools to choose from, such as tools that can be integrated into layout tools, or tools used separately for signal integrity analysis. As long as chip designers start to pay attention to inductance L and change their way of thinking, this is completely feasible. For traditional silicon extraction tools, they must also start to pay attention to this aspect. Because as the size of repeaters increases, circuit lengths increase, and speeds improve, they are getting closer and closer to the wavelength or one-tenth of the wavelength. We must consider this aspect, otherwise we will face signal integrity issues."

Compared to the past, architects need more help. "Everyone needs a system planner," Park said, "The design is not just a single chip, but three integrated chips. From a higher level, you need a system planner to integrate these chip components, optimize their placement, pay attention to thermal design and power transmission, and create an optimized 3D plan. Then you can use one tool to design digital chip components, use another tool to design analog chip components, and finally package. From a tool perspective, system-level planning has made great progress, but we are just expanding their databases and adding new features."

The biggest change may be at the organizational level. Mastroianni said: "In the past, packaging designers never communicated with architects. Now there must be this communication. Which implementation technology will be chosen? How will thermal issues be handled? What kind of packaging technology will be used? Is it a silicon-based repeater or an organic repeater? Because there are countless scenarios, analysis needs to be done as early as possible. How to divide the system or subsystem into many chip sets? At the architectural decomposition level, you need to consider stress analysis at least. When you start physical design, packaging designers need to work with chip designers to complete I/O planning. In addition, testing methods should also be considered. Test engineers need to cooperate with packaging engineers to discuss what testing strategies are used in the chip set, and how to connect them in the packaging."Conclusion

EDA Corporation has made improvements to existing tools to achieve and verify 2.5D systems. However, these tools may not be sufficient to make 2.5D integration mainstream, as the tools may not perfectly align with the structural organization of the design team. Although there is no consensus on the optimal organizational structure, they ultimately need to work together and collaborate. Problems often lie in the details, and with the current methodologies, there are many pitfalls and unknowns that could lead to potential disasters at any time.

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